1. Field of the Invention
The present invention, generally, relates to a process for making organic chip packages and, more particularly, to a new and improved technique by which chips are attached to substrates and substrates are attached to circuit boards that permit the substrates to be removed without affecting other attachments.
In recent years, much effort has been devoted to problems that are involved in soldering laminate chip carriers to circuit boards, and happily, many rather sophisticated problems have been solved by recognizing some of the characteristics and requirements for making the soldering connections between the chip carriers and the circuit boards. Then, before the rejoicing died down, it appeared that all of these efforts were for naught when it was found that in soldering a chip module to a mother board, the solder connections between the chip and the chip carrier in the chip module were damaged severely or destroyed completely.
It has become increasingly evident that chip modules must be removed or de-soldered from a mother board for replacement with a new or updated module or when it becomes necessary to perform other repair work. During these activities, the soldering connections between the chip and the chip carrier of the new module, or other neighboring modules on the mother board, are damaged due to thermal exposure.
An example of the type of soldering connection that is damaged by such repairs or rework is U.S. Pat. No. 4,480,261 to Hattori et al., which explains the problem and describes the complexity involved in developing a solution. This patent is of absolutely no relevance to the present invention, however.
Currently, chips are provided during manufacture with balls of solder at points where they are to be attached to a carrier, module or substrate. These balls are a Pb-Sn solder used by some manufacturers in a technique known as Controlled Collapse Chip Connection (called "C-4").
It is connections involving the C-4 balls that are damaged during heating when a module is removed or otherwise involved in a process requiring a temperature above 183 degrees C. When these connections are subjected to these temperatures, there is flow of molten Sn--Pb eutectic solder into the interface that exists between the chip and the encapsulant material.
In addition to the above identified solder flow during rework temperatures, residual moisture within the chip-carrier assembly will be converted to vapor causing large scale flow of the solder into the chip/encapsulant interface. When this occurs, severe shorting results.
2. Description of the Prior Art
The Assignee of the present invention has devoted substantial research seeking a way to avoid these activities that result in damage to soldering connections between substrates and circuit boards, such as:
U.S. Pat. No. 4,914,814 to Behun et al. describes a process using miniature pins with solder to form a bonding connection.
U.S. Pat. No. 5,060,844 to Behun et al. which describes a use of two solders and an epoxy layer about one of them.
IBM Technical Disclosure Bulletin, Vol. 14, No. 8, January 1972, by Martyak et al. describes the use of two solders in a distinctive structural arrangement to maintain separation.
While the methods and circuit arrangements of the prior art first appearances have similarities with the present invention, they differ in material respects. These differences, as will be described in more detail hereinafter, are essential for the effective use of the invention and which admit of the advantages that are not available with the prior art.